Tech article
Store Load Reordering: x86 vs ARM64, and the Bug Intel Was Hiding
Community description: The same lock-free C program runs clean on Intel for hours and fails on ARM64 in a minute. The source is identical. This is store→load reordering — why x86's TSO hides it, why ARM64 exposes it, and what a fence actually does — with a real litmus.
Dev.to | Sep 12, 2026 | Harrison Guo
Automated excerpt
Now the timeline that was forbidden is trivial: Thread 1 loads Y (still 0), Thread 2 loads X (still 0), then both stores land. r1 == 0 && r2 == 0. So the load happened before Thread 2's Y = 1 (that's the only way Y could still be 0), which means Thread 2's Y = 1 — and therefore everything before it on Thread 2, including its load r2 = X — happened after X = 1 was visible. So r2 must read 1. r1 == 0 forces r2 == 1; both-zero cannot occur.
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