When Ldaxr Doesn't Work: Exclusive Accesses and Cacheability on AArch64

Automated excerpt

We will cover an exciting combination of areas, which include: spin locks, exception handling, virtual memory, memory types, memory attributes, cacheability, the differences between QEMU and real hardware, and most notably, how exclusive memory operations work. Memory attributes are configured via the Memory Attribute Indirection Register (MAIR_EL1 for EL1). Currently, floss only configures two sets of memory attributes, one for Device memory and one for Normal memory.

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